1. Field of the Invention
The present invention relates to a novel trench capacitor and a method for manufacturing the same.
2. Description of Prior Art
A number of manufacturing methods for trench capacitors is known in the state of the art, in which a deep trench is etched into a substrate, usually a p-substrate, and an oxide collar is formed either during or after the etching process, which switches off the vertical, parasitary field effect transistor, which develops later. The bottom electrode of such a trench capacitor is usually generated by diffusing As into the substrate. Alternatively, a buried doped layer, which is an n+-layer, when a p-substrate is used and which is referred to as a so-called buried plate, may be used as a bottom electrode. In the trench, the storage dielectric and, onto the storage dielectric, the counterelectrode and/or the top electrode are deposited. As a rule, the top electrode is a polycrystalline semiconductor material, which fills the trench remaining as a result of the deposition of the storage dielectric. Subsequently, the top electrode is etched back, and, via a connection area, which is usually referred to as a buried strap, is connected to the assigned selection transistor of a DRAM cell. In such an application of the trench capacitor in a DRAM cell, the charge is stored in the top electrode.
It is the object of the present invention to provide a trench capacitor having an increased capacity and a method for manufacturing such a trench capacitor.
According to a first aspect of the present invention this object is achieved by a trench capacitor having a first capacitor electrode, a second capacitor electrode, and a dielectric arranged between the capacitor electrodes. The first capacitor electrode comprises a tube-like structure projecting into a substrate. The second capacitor electrode comprises a first section, which is opposite to the tube-like structure with the dielectric of the internal side arranged therebetween, and further comprises a second section, which is opposite to the tube-like structure with the dielectric of the external side arranged therebetween.
According to a second aspect of the invention this object is achieved by a method for manufacturing a trench capacitor including the steps of:
generating a trench in a substrate of a first doping type, wherein a section of a second doping type adjoins a portion of the trench;
generating, at least on the side walls of the trench, a first dielectric layer;
generating a conductive layer on the first dielectric layer;
generating a second dielectric layer on the conductive layer; and
generating conductive areas on the second dielectric layer, which are conductively connected to the section of a second doping type.
The inventive trench capacitor, which, in particular, is suitable for use as a storage capacitor, e.g. of a DRAM cell, thus comprises an upper and/or top electrode, which consists of a tube-shaped structure, which, both on its inside and outside, comprises a storage dielectric and a counterelectrode. Thus, compared to conventional trench capacitors, the capacity may be approximately doubled by the increase of the capacitor surface. Moreover, the region, in which the collar oxide is formed, may be used for the capacitor.
The inventive trench capacitor is scalable up to structure sizes of 100 nm and ensures a low lead resistance. As described, owing to the special structure, the capacitor surface, and, thus the capacitance, is about two times as large as are conventional structures.
In the inventive method for manufacturing the trench capacitor, use may be made of standard processes, as are employed in the manufacture of conventional trench capacitors, until the upper electrode is generated. Then, instead of a thick upper electrode, which fills the whole of the trench, only a relatively thin layer, in the magnitude of 20 nm, of a well-conducting material, e.g. metal, is deposited. Subsequently, a spacer etching will be carried out, which again opens this layer at the lower end of the trench capacitor. After depositing a second storage dielectric and a thin protective layer, which will act as an electrode later on, a spacer etching is again carried out, such that the bottom electrode is exposed again. A deposition of a polycrystalline semiconductor material, preferably polysilicon, now connects the inner electrode to the substrate, i.e. the doped areas of the same, which form the bottom electrode. After a step of recess-etching the polycrystalline filling, an insulator will be applied in order to insulate the inner counterelectrode sections lying opposite to the upper electrode from a conductive polycrystalline semiconductor material, which is then to be inserted into the recess-etched section of the trench. This polycrystalline semiconductor material, which is to be inserted, serves as a connection area for the top electrode in the form of a buried strap. Subsequently, standard processes may be used to finish the DRAM cell.
Further developments of the present invention are set forth in the dependent claims.